As cell dimensions in memory devices scale to smaller dimensions, the integrity of data storage is challenged. In particular, the raw bit error rate in non-volatile memory devices such as NAND flash memory has been observed to increase with decreasing cell size. NAND flash architecture is structured such that memories are accessed much like block devices including hard disks or memory cards in which a block may contain multiple pages. NAND technology relies on an error correction code (ECC) process to compensate for bits that may spontaneously fail during normal device operation.
In order to achieve a tolerable bit error rate, an error correction engine is typically employed at the system level. The most common ECC that has been employed in recent generations of NAND products uses a so-called BCH code (the acronym is derived from the inventor's names Bose, Ray-Chaudhuri, and Hocquenghem). However, BCH code may not be able to deliver the error correction capability that may be required in future generation NAND products as the memory cell size continues to scale to smaller dimensions.
On the other hand, error codes such as the low density parity check (LDPC) provide greater capability, but require that a NAND memory provide data in a different manner than conventional user data. Unlike the BCH method, which uses “hard decoding,” some codes including LDPC enable “soft decoding,” where, in addition to each bit value, the decoder can also estimate the bit's reliability using other data. Soft decoding can yield significant correction capability gains over hard decoding, because the decoder knows which bits are more likely to be flipped and can use this information in its correction algorithms. In particular, the LPDC procedure requires that state confidence data be provided. The state confidence data refers to data that reflects the reliability of data to indicate state of the memory cell. In error correction approaches that employ the LDPC scheme, an ECC engine may convert the state confidence information into conventional user data.
In order to achieve efficient generation of state confidence data for non-volatile memory devices, such as NAND storage devices, present day schemes may require modification. Accordingly, there may be a need for improved techniques and apparatus to solve these and other problems.